3.7 VEDIC MULTIPLIER

 Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). Here we are going to design the high speed Vedic Multiplier using  Vedic Mathematics that have been modified to improve performance. A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in general processors. Vedic Mathematics has a unique technique of calculations based on 16 Sutras.

I had implemented 4 bit vedic multiplier using Ripple carry adder,we can also use any type of adders which we discussed above. 

DIAGRAM:

2 BIT VEDIC MULTIPLIER:

 

4 BIT VEDIC MULTIPLIER: 

 

PROGRAM:

4 BIT VEDIC MULTIPLIER:

 

module vm4(s, a, b);

input [3:0] a;

input [3:0] b;

output [7:0] s;

wire c1,c2,c3;

wire [3:0]v;

wire [3:0]j;

wire [3:0]k;

wire [3:0]m;

wire [3:0]r;

wire [3:0]g;

wire [3:0]n;

wire [3:0]y;

wire [3:0]p;

vm2 v1(v[3:0],a[1:0],b[1:0]);

vm2 v2(j[3:0],a[1:0],b[3:2]);

vm2 v3(k[3:0],a[3:2],b[1:0]);

vm2 v4(m[3:0],a[3:2],b[3:2]);

adder a1(r[3:0],c1,k[3:0],j[3:0],1'b0);

assign s[1:0] = v[1:0];

assign g[1:0] = v[3:2];

assign g[2] = 1'b0;

assign g[3] = 1'b0;

adder a2(n[3:0],c2,r[3:0],g[3:0],1'b0);

assign s[3:2] = n[1:0];

assign y[1:0] = n[3:2];

assign y[2] = c1;

assign y[3] = 1'b0;

adder a3(p[3:0],c3,m[3:0],y[3:0],1'b0);

assign s[7:4] = p[3:0];

endmodule

2 BIT VEDIC MULTIPLIER:

module vm2(c, a, b);

    output [3:0] c;

    input [1:0] a;

    input [1:0] b;

    wire [3:0] temp;

assign c[0] = a[0]&b[0];

assign temp[0] = a[1]&b[0];

assign temp[1] = a[0]&b[1];

assign temp[2] = a[1]&b[1];

half a1(temp[0],temp[1],c[1],temp[3]);

half a2(temp[2],temp[3],c[2],c[3]);

endmodule

 RIPPLE CARRY ADDER:

 

module adder(sum,carry,a,b,cin);

output [3:0]sum;

output carry;

input [3:0]a,b;

input cin;

wire d1,d2,d3;

 full_adder g1(sum[0],d1,a[0],b[0],cin);

 full_adder g2(sum[1],d2,a[1],b[1],d1);

 full_adder g3(sum[2],d3,a[2],b[2],d2);

 full_adder g4(sum[3],carry,a[3],b[3],d3);

endmodule

FULL ADDER

module full_adder(sum,carry,a,b,cin);

output  sum;

output carry;

input a,b;

input cin;

assign sum = a^b^cin;

assign carry = (a&b)|(cin &(a|b));

endmodule

 HALF ADDER

 

module half(a,b,sum,carry);

input a,b;

output sum;

output carry;

assign sum = a^b;

assign carry = a&b;

endmodule