2.5 Carry Select adder:
The
carry-select adder generally consists of two ripple carry adders and a multiplexer. Adding two n-bit numbers with a carry-select adder is done
with two adders (therefore two ripple carry adders) in order to perform the
calculation twice, one time with the assumption of the carry being zero and the
other assuming one. After the two results are calculated, the correct sum, as
well as the correct carry, is then selected with the multiplexer once the
correct carry is known.
Verilog:
Program:
Carry
Select adder:
module csel4(sum, carry,
a, b, cin);
output [3:0]sum;
output carry;
input [3:0]a,b;
input cin;
wire [3:0]sv,sk;
wire cv,ck;
rca
g1(sv[3:0],cv,a[3:0],b[3:0],1'b0);
rca
g2(sk[3:0],ck,a[3:0],b[3:0],1'b1);
mux
g3(sum[0],cin,sv[0],sk[0]);
mux g4(sum[1],cin,sv[1],sk[1]);
mux
g5(sum[2],cin,sv[2],sk[2]);
mux
g6(sum[3],cin,sv[3],sk[3]);
mux
g7(carry,cin,cv,ck);
endmodule
Ripple
Carry Adder:
module rca(sum,carry,a,b,cin);
output [3:0]sum;
output carry;
input [3:0]a,b;
input cin;
wire d1,d2,d3;
full_adder g1 (sum[0],d1,a[0],b[0],cin);
full_adder g2 (sum[1],d2,a[1],b[1],d1);
full_adder g3 (sum[2],d3,a[2],b[2],d2);
full_adder g4 (sum[3],carry,a[3],b[3],d3);
endmodule
Full
Adder:
module
full_adder(sum,carry,a,b,cin);
output sum,carry;
input a,b,cin;
wire carry1,carry2,sum1;
half_adder
g1(sum1,carry1,a,b);
half_adder
g2(sum,carry2,cin,sum1);
or
g3(carry,carry1,carry2);
endmodule
Half
Adder:
module
half_adder(sum,carry,a,b);
output sum,carry;
input a,b;
assign sum = a^b;
assign carry = a&b;
endmodule
2:1
Multiplexer:
module mux(out,s,a,b);
output out;
input a,b,s;
reg out;
always@(a,b,s)
begin
case(s)
1'b0:out=a;
1'b1:out=b;
endcase
end
endmodule
VHDL:
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity csel is
port(a : in STD_LOGIC_VECTOR (3 downto
0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
yout : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end csel;
architecture Behavioral of csel is
component mux
Port ( i0,i1 : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component rca
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
yout : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end component;
signal cv,ck: STD_LOGIC;
signal sv,sk: STD_LOGIC_VECTOR (3 downto
0);
begin
ad0:rca port map(a(3 downto 0),b(3
downto 0),'0',sv(3 downto 0),cv);
ad1:rca port map(a(3 downto 0),b(3
downto 0),'1',sk(3 downto 0),ck);
m0:mux port
map(sv(0),sk(0),cin,yout(0));
m1:mux port
map(sv(1),sk(1),cin,yout(1));
m2:mux port
map(sv(2),sk(2),cin,yout(2));
m3:mux port map(sv(3),sk(3),cin,yout(3));
m4:mux port map(cv,ck,cin,cout);
end Behavioral;
Ripple
Carry Adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rca is
Port ( a : in STD_LOGIC_VECTOR (3 downto
0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
yout : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end rca;
architecture Behavioral of rca is
component fulladd
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
yout : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
signal c1,c2,c3: STD_LOGIC;
begin
ad0:fulladd port
map(a(0),b(0),cin,yout(0),c1);
ad1:fulladd port
map(a(1),b(1),c1,yout(1),c2);
ad2:fulladd port map(a(2),b(2),c2,yout(2),c3);
ad3:fulladd port
map(a(3),b(3),c3,yout(3),cout);
end Behavioral;
Full
Adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladd is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
yout : out STD_LOGIC;
cout : out STD_LOGIC);
end fulladd;
architecture Behavioral of fulladd is
begin
yout<=a xor b xor cin;
cout<=(a and b) or (cin and (a xor
b));
end Behavioral;
2:1
Multiplexer:
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity mux is
Port ( i0,i1 : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC);
end mux;
Architecture Behavioral of mux is
begin
with s select
y<= i0 when '0',
i1 when '1',
'0' when others;
end Behavioral;
2.6 Carry Save adder:
When three or more operands are to be added simultaneously
(e.g., in multiplication) using two-operand adders, the time-consuming
carry-propagation must be repeated several times. If the number of operands is k,
then carries have to propagate ( k ?1) times. Several techniques for
multiple operand addition that attempt to lower the carry-propagation penalty
have been proposed and implemented. The technique that is most commonly used is
carry-save addition. In carry-save addition, we let the carry propagate
only in the last step, while in all the other steps we generate a partial sum
and a sequence of carries separately. Thus, the basic carry-save adder (CSA)
accepts three n-bit operands and generates two n-bit results, an n-bit
partial sum, and an n-bit carry. A second CSA accepts this two
bit-sequences and another input operand, and generates a new partial sum and
carry. A CSA is therefore, capable of reducing the number of operands to be
added from 3 to 2, without any carry propagation.
A carry-save adder may
be implemented in several different ways. In the simplest implementation, the
basic element of the carry-save adder is a full adder with three inputs, x,
y, and z, whose arithmetic operation can be described by
where s and c
are the sum and carry outputs, respectively. Their values are
The outputs are the
weighted binary representation of the number of 1 s in the inputs.
Verilog
Program
module
CSA(A,B,Ci,So,Co);
output [7:0] So;
output Co;
input [7:0] A,B;
input Ci;
wire [3:0]
stemp1,stemp0;
wire c4;
wire c80,c81;
RCA
RCAin(A[3:0],B[3:0],Ci, So[3:0],c4);
RCA RCA1
(A[7:4],B[7:4],1'b1,stemp1,c81);
RCA RCA0
(A[7:4],B[7:4],1'b0,stemp0,c80);
assign So[7:4] =
c4?stemp1:stemp0;
assign Co=
c4?c81:c80;
endmodule
VHDL:
Program:
library IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.NUMERIC_STD.ALL;
entity csaa is
port( a:in
std_logic_vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
carry:in std_logic;
outsum:out std_logic_vector(3 downto
0);
outcarry:out std_logic);
end csaa;
architecture
Behavioral of csaa is
signal
c0,c1,sum0,sum1:std_logic_vector(3 downto 0);
signal
carry0,carry1:std_logic;
component fulladder
is
port(a,b,cin :in
std_logic;
sum,cout: out std_logic);
end component;
begin
carry0<=carry;
carry1<=not
carry;
fa01:fulladder port
map(a(0),b(0),carry0,sum0(0),c0(0));
fa02:fulladder port
map(a(1),b(1),c0(0),sum0(1),c0(1));
fa03:fulladder port
map(a(2),b(2),c0(1),sum0(2),c0(2));
fa04:fulladder port
map(a(3),b(3),c0(2),sum0(3),c0(3));
fa11:fulladder port
map(a(0),b(0),carry1,sum1(0),c1(0));
fa12:fulladder port
map(a(1),b(1),c1(0),sum1(1),c1(1));
fa13:fulladder port
map(a(2),b(2),c1(1),sum1(2),c1(2));
fa14:fulladder port
map(a(3),b(3),c1(2),sum1(3),c1(3));
process(carry)
begin
if (carry=0) then
outcarry<=c0(3);
outsum<=sum0;
else
outcarry<=c1(3);
outsum<=sum1;
end if;
end process;
end Behavioral;
Sub Program for
Full Adder
library IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
Port ( a : in
STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out
STD_LOGIC;
cout : out
STD_LOGIC);
end fulladder;
architecture
Behavioral of fulladder is
begin
sum<= a xor b
xor cin;
cout<=(a and
b)or(b and cin)or(cin and a);
end Behavioral;
2.7 Kogge Stone Adders
The Kogge Stone Adders
are a prefix form of carry look ahead of carry look ahead adders.
Verilog
Program:
module kogge_stone (x,
y, sum, cin, cout);
input [7:0] x, y;
output [7:0] sum;
input cin;
output cout;
wire [7:0] G_Z, P_Z, G_A, P_A, G_B, P_B, G_C, P_C;
gray_cell level_0A(cin, P_Z[0], G_Z[0],
G_A[0]);
black_cell level_1A(G_Z[0], P_Z[1], G_Z[1],
P_Z[0], G_A[1], P_A[1]);
black_cell level_2A(G_Z[1], P_Z[2], G_Z[2],
P_Z[1], G_A[2], P_A[2]);
black_cell level_3A(G_Z[2], P_Z[3], G_Z[3],
P_Z[2], G_A[3], P_A[3]);
black_cell level_4A(G_Z[3], P_Z[4], G_Z[4],
P_Z[3], G_A[4], P_A[4]);
black_cell level_5A(G_Z[4], P_Z[5], G_Z[5],
P_Z[4], G_A[5], P_A[5]);
black_cell level_6A(G_Z[5], P_Z[6], G_Z[6],
P_Z[5], G_A[6], P_A[6]);
black_cell level_7A(G_Z[6], P_Z[7], G_Z[7],
P_Z[6], G_A[7], P_A[7]);
gray_cell level_1B(cin, P_A[1], G_A[1],
G_B[1]);
gray_cell level_2B(G_A[0], P_A[2], G_A[2],
G_B[2]);
black_cell level_3B(G_A[1], P_A[3], G_A[3],
P_A[1], G_B[3], P_B[3]);
black_cell level_4B(G_A[2], P_A[4], G_A[4],
P_A[2], G_B[4], P_B[4]);
black_cell level_5B(G_A[3], P_A[5], G_A[5],
P_A[3], G_B[5], P_B[5]);
black_cell level_6B(G_A[4], P_A[6], G_A[6],
P_A[4], G_B[6], P_B[6]);
black_cell level_7B(G_A[5], P_A[7], G_A[7],
P_A[5], G_B[7], P_B[7]);
gray_cell level_3C(cin, P_B[3], G_B[3],
G_C[3]);
gray_cell level_4C(G_A[0], P_B[4], G_B[4],
G_C[4]);
gray_cell level_5C(G_B[1], P_B[5], G_B[5],
G_C[5]);
gray_cell level_6C(G_B[2], P_B[6], G_B[6],
G_C[6]);
black_cell level_7C(G_B[3], P_B[7], G_B[7],
P_B[3], G_C[7], P_C[7]);
gray_cell level_7D(cin, P_C[7], G_C[7], cout);
and_xor level_Z0(x[0], y[0], P_Z[0], G_Z[0]);
and_xor level_Z1(x[1], y[1], P_Z[1], G_Z[1]);
and_xor level_Z2(x[2], y[2], P_Z[2], G_Z[2]);
and_xor level_Z3(x[3], y[3], P_Z[3], G_Z[3]);
and_xor level_Z4(x[4], y[4], P_Z[4], G_Z[4]);
and_xor level_Z5(x[5], y[5], P_Z[5], G_Z[5]);
and_xor level_Z6(x[6], y[6], P_Z[6], G_Z[6]);
and_xor level_Z7(x[7], y[7], P_Z[7], G_Z[7]);
xor(sum[0], cin, P_Z[0]);
xor(sum[1], G_A[0], P_Z[1]);
xor(sum[2], G_B[1], P_Z[2]);
xor(sum[3], G_B[2], P_Z[3]);
xor(sum[4], G_C[3], P_Z[4]);
xor(sum[5], G_C[4], P_Z[5]);
xor(sum[6], G_C[5], P_Z[6]);
xor(sum[7], G_C[6], P_Z[7]);
endmodule
black
cell:
module black_cell(Gkj,
Pik, Gik, Pkj, G, P);
input Gkj, Pik, Gik,
Pkj;
output G, P;
wire Y;
and(Y, Gkj, Pik);
or(G, Gik, Y);
and(P, Pkj, Pik);
endmodule
gray
cell:
module gray_cell(Gkj,
Pik, Gik, G);
input Gkj, Pik, Gik;
output G;
wire Y;
and(Y, Gkj, Pik);
or(G, Y, Gik);
endmodule
and_xor
module and_xor(a, b, p,
g);
input a, b;
output p, g;
xor(p, a, b);
and(g, a, b);
endmodule
2.8 Ling adder
Ling adders are a variation of the
carry-look-ahead adders. They use a simpler version of the group-generated
carry signal and thus provide an opportunity to reduce the associated delay. We
will see the principle behind Ling adders through a simple example. Suppose
that we start with a carry-look-ahead adder with groups of size 2, i.e., we
produce the signals G 1 : 0, P 1
: 0, G 3: 2, P 3:2
and so on. The outgoing carry for position 3 can be expressed as
Where
We either assume that c 0=0
or set G 0 =x 0 y 0 +P
0 c 0. Expressing G 3: 0
in terms of the individual carry generate and propagate signals we obtain
Since G 3 P 3=
G 3 all terms in the above equation have P 3
as a common factor, and we can therefore rewrite the expression for G 3:0
as
Verilog:
Program:
module
ling4(s,cout,i1,i2,h0);
output [3:0] s;
output cout;
input [3:0] i1;
input [3:0] i2;
input h0;
wire [3:0] t;
wire [3:0] g;
wire [4:1] h;
assign g[3:0]=i1[3:0] & i2[3:0];
assign t[3:0]=i1[3:0] | i2[3:0];
assign h[1]=g[0] | (h0&t[0]);
assign h[2]=g[1] | g[0] | (t[0]&h0));
assign h[3]=g[2] | g[1] | (g[0]&t[1]) |
(t[0]&t[1]&h0);
assign h[4]=g[3] | g[2] | (g[1]&t[2]) |
(g[0]&t[1]&t[2]) | (t[0]&t[1]&t[2]&h0);
assign cout=h[4] & t[3];
assign s[0]=(t[0] ^
h[1]) | (h0 & t[0] & g[0]);
assign s[3:1]=(t[3:1] ^ h[4:2]) | (h[3:1] &
t[2:0] & g[3:1]);
endmodule
2.9
SPST adder
The first
case illustrates a transient state in which the spurious transitions of carry
signals occur in the MSP though the final result of the MSP are unchanged. The second
and third cases describe the situations of one negative operand adding another
positive operand without and with carry from LSP, respectively. Moreover, the fourth
and fifth cases respectively demonstrate the conditions of two negative
operands addition without and with carry-in from LSP. In those cases, the
results of the MSP are predictable, therefore the computations in the MSP are
useless and can be neglected. Eliminating those spurious computations will not
only save the power consumed inside the adder but also decrease the glitching
noises which will affect the next arithmetic circuits.
VHDL:
Program:
Main:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SPST is
Port(Clk:in std_logic;
A:in std_logic_vector(31 downto
0);
B:in std_logic_vector(31 downto
0);
Cin:in std_logic;
Sum:out std_logic_vector(31
downto 0);
Cout:out std_logic);
end SPST;
architecture Behavioral of SPST is
component Detection_logic32
port(clk:in std_logic;
a:in std_logic_vector(31 downto
0);
b:in std_logic_vector(31 downto
0);
C_LSP:in std_logic;
close:out std_logic;
err_ctr:out std_logic;
sign:out std_logic);
end component;
component adder16
port(a:in std_logic_vector(15 downto 0);
b:in std_logic_vector(15 downto
0);
cin:in std_logic;
yout:out std_logic_vector(15 downto 0);
cout:out std_logic);
end component;
component Latch16
port(clk,rst:in std_logic;
D:in std_logic_vector(15 downto
0);
Q:out std_logic_vector(15 downto 0));
end
component;
component Sign_Extend16
Port(S:in std_logic_vector(15 downto 0);
Sign:in std_logic;
Carr_ctrl:in std_logic;
PS:out std_logic_vector(16 downto 0));
end component;
signal carr_ctr,close,A_and,B_and,sign:std_logic;
signal t,t1,t2,t3,t4,C1,C_LSP:std_logic;
signal C : std_logic:='0';
signal
S_LSP,A1,B1,PS:std_logic_vector(15 downto 0);
signal S_MSP:std_logic_vector(16 downto
0);
begin
L1: Detection_Logic32 port map (Clk,A(31
downto 0),B(31 downto 0),C,close,carr_ctr,sign);
A_and<= a(31) and a(30) and a(29) and
a(28) and a(27) and a(26) and a(25) and a(24) and a(23) and a(22) and a(21) and
a(20) and a(19) and a(18) and a(17) and a(16) and a(15) and a(14) and a(13) and
a(12) and a(11) and a(10) and a(9) and a(8) and a(7) and a(6) and a(5) and a(4)
and a(3) and a(2) and a(1) and a(0);
B_and<= b(31) and b(30) and b(29) and
b(28) and b(27) and b(26) and b(25) and b(24) and b(23) and b(22) and b(21) and
b(20) and b(19) and b(18) and b(17) and b(16) and b(15) and b(14) and b(13) and
b(12) and b(11) and b(10) and b(9) and b(8) and b(7) and b(6) and b(5) and b(4)
and b(3) and b(2) and b(1) and b(0);
L2: Latch16 port map ( clk,close,A(31
downto 16),A1);
L3: Latch16 port map ( clk,close,B(31
downto 16),B1);
L4: adder16 port map
(A1,B1,C_LSP,PS,C1);
L5: Sign_Extend16 port map
(PS,sign,carr_ctr,S_MSP);
L6: adder16 port map (A(15 downto
0),B(15 downto 0),Cin,S_LSP,C_LSP);
t<= C_LSP and close;
t1<= A_and and B_and ;
t2<= A_and or B_and ;
t3<=t2 and t;
t4<= t1 or t3;
Cout<= t4 or C1;
Sum<= S_MSP(15 downto 0) & S_LSP;
end Behavioral;
latch:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Latch16 is
port(clk,rst:in std_logic;
D:in std_logic_vector(7 downto 0);
Q:out std_logic_vector(7 downto 0));
end Latch16;
architecture Behavioral of Latch16 is
begin
process(clk,rst,D)
begin
if
rst='1' then
Q<=X"00";
elsif clk='1' and clk' event then
Q<=D;
end if;
end process;
end Behavioral;
Sign Extension:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Sign_Extend16 is
Port(S:in std_logic_vector(15 downto 0);
Sign:in std_logic;
Carr_ctrl:in std_logic;
PS:out std_logic_vector(16 downto 0));
end Sign_Extend16;
architecture Behavioral of Sign_Extend16
is
begin
Process(S,sign,Carr_ctrl)
begin
if Carr_ctrl='1' then
PS<= Sign & S;
else
PS<= '0' & S;
end if;
end Process;
end Behavioral;
Detection logic:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Detection_Logic32 is
port(clk:in std_logic;
a:in std_logic_vector(31 downto 0);
b:in std_logic_vector(31 downto 0);
C_LSP:in std_logic;
close:out std_logic;
err_ctr:out std_logic;
sign:out std_logic);
end Detection_Logic32;
architecture Behavioral of
Detection_Logic32 is
signal O1,O2,O3:std_logic;
signal A1,A2:std_logic;
signal AA,AN,BA,BN:std_logic;
signal N1,Nd,X:std_logic;
signal
BN1,BN2,BN3,BN4,BN5,BN6,BN7,BN8,BN9,BN10,BN11,BN12,BN13,BN14,BN15,BN16,BN17,BN18,BN19,BN20,BN21,BN22,BN23,BN24,BN25,BN26,BN27,BN28,BN29,BN30:std_logic;
signal AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30:std_logic;
begin
AN1<= a(31) nor a(30);
AN2<= AN1 nor a(29);
AN3<= AN2 nor a(28);
AN4<= AN3 nor a(27);
AN5<= AN4 nor a(26);
AN6<= AN5 nor a(25);
AN7<= AN6 nor a(24);
AN8<= AN7 nor a(23);
AN9<= AN8 nor a(22);
AN10<= AN9 nor a(21);
AN11<= AN10 nor a(20);
AN12<= AN11 nor a(19);
AN13<= AN12 nor a(18);
AN14<= AN13 nor a(17);
AN15<= AN14 nor a(16);
AN16<= AN15 nor a(15);
AN17<= AN16 nor a(14);
AN18<= AN17 nor a(13);
AN19<= AN18 nor a(12);
AN20<= AN19 nor a(11);
AN21<= AN20 nor a(10);
AN22<= AN21 nor a(9);
AN23<= AN22 nor a(8);
AN24<= AN23 nor a(7);
AN25<= AN24 nor a(6);
AN26<= AN25 nor a(5);
AN27<= AN26 nor a(4);
AN28<= AN27 nor a(3);
AN29<= AN28 nor a(2);
AN30<= AN29 nor a(1);
AN<= AN30 nor a(0);
BN1<= b(31) nor b(30);
BN2<= BN1 nor b(29);
BN3<= BN2 nor b(28);
BN4<= BN3 nor b(27);
BN5<= BN4 nor b(26);
BN6<= BN5 nor b(25);
BN7<= BN6 nor b(24);
BN8<= BN7 nor b(23);
BN9<= BN8 nor b(22);
BN10<= BN9 nor b(21);
BN11<= BN10 nor b(20);
BN12<= BN11 nor b(19);
BN13<= BN12 nor b(18);
BN14<= BN13 nor b(17);
BN15<= BN14 nor b(16);
BN16<= BN15 nor b(15);
BN17<= BN16 nor b(14);
BN18<= BN17 nor b(13);
BN19<= BN18 nor b(12);
BN20<= BN19 nor b(11);
BN21<= BN20 nor b(10);
BN22<= BN21 nor b(9);
BN23<= BN22 nor b(8);
BN24<= BN23 nor b(7);
BN25<= BN24 nor b(6);
BN26<= BN25 nor b(5);
BN27<= BN26 nor b(4);
BN28<= BN27 nor b(3);
BN29<= BN28 nor b(2);
BN30<= BN29 nor b(1);
BN<= BN30 nor b(0);
AA<= a(30) and a(29) and a(28) and a(27) and a(26) and a(25) and
a(24) and a(23) and a(22) and a(21) and a(20) and a(19) and a(18) and a(17) and
a(16) and a(15) and a(14) and a(13) and a(12) and a(11) and a(10) and a(9) and
a(8) and a(7) and a(6) and a(5) and a(4) and a(3) and a(2) and a(1) and a(0);
BA<= b(30) and b(29) and b(28) and b(27) and b(26) and b(25) and
b(24) and b(23) and b(22) and b(21) and b(20) and b(19) and b(18) and b(17) and
b(16) and b(15) and b(14) and b(13) and b(12) and b(11) and b(10) and b(9) and
b(8) and b(7) and b(6) and b(5) and b(4) and b(3) and b(2) and b(1) and b(0);
O1<=AA or AN;
O2<=AA or BA;
X<= AA xor BA xor C_LSP;
A1<=AA and BA and C_LSP;
O3<=BN or BA;
N1<= not(C_LSP);
A2<= N1 and O2;
Nd<=O3 and O1;
err_ctr<=O1 and X and A2;
sign<=A2 or A1;
close<= clk and Nd;
end Behavioral;
RIPPLE
CARRY ADDER:
16
BIT:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder16 is
Port ( a : in STD_LOGIC_VECTOR (15
downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
cin : in STD_LOGIC;
yout : out STD_LOGIC_VECTOR (15 downto 0);
cout : out STD_LOGIC);
end adder16;
architecture Behavioral of adder16 is
component adder8
Port ( a : in STD_LOGIC_VECTOR (7 downto
0);
b : in STD_LOGIC_VECTOR (7 downto 0);
cin : in STD_LOGIC;
yout : out STD_LOGIC_VECTOR (7 downto 0);
cout : out STD_LOGIC);
end component;
signal c1: STD_LOGIC;
begin
ad0:adder8 port map(a(7 downto 0),b(7
downto 0),cin,yout(7 downto 0),c1);
ad1:adder8 port map(a(15 downto 8),b(15
downto 8),c1,yout(15 downto 8),cout);
end Behavioral;
8
BIT:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder8 is
Port ( a : in STD_LOGIC_VECTOR (7
downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
cin : in STD_LOGIC;
yout : out STD_LOGIC_VECTOR (7 downto 0);
cout : out STD_LOGIC);
end adder8;
architecture Behavioral of adder8 is
component adder4
Port ( a : in STD_LOGIC_VECTOR (3 downto
0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
yout : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end component;
signal c1: STD_LOGIC;
begin
ad0:adder4 port map(a(3 downto 0),b(3
downto 0),cin,yout(3 downto 0),c1);
ad1:adder4 port map(a(7 downto 4),b(7
downto 4),c1,yout(7 downto 4),cout);
end Behavioral;
4
BIT:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder4 is
Port ( a : in STD_LOGIC_VECTOR (3 downto
0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
yout : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end adder4;
architecture Behavioral of adder4 is
component fulladd
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
yout : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
signal c1,c2,c3: STD_LOGIC;
begin
ad0: fulladd port map(a(0),b(0),cin, yout(0),c1);
ad1:fulladd port
map(a(1),b(1),c1,yout(1),c2);
ad2:fulladd port
map(a(2),b(2),c2,yout(2),c3);
ad3:fulladd port
map(a(3),b(3),c3,yout(3), cout);
end Behavioral;
Full
Adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladd is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
yout : out STD_LOGIC;
cout : out STD_LOGIC);
end fulladd;
architecture Behavioral of fulladd is
begin
yout<=a xor b xor cin;
cout<=(a and b) or (cin and (a xor
b));
end Behavioral;
