The storage elements
used in clocked sequential circuits are called flip flops. A flip flop is a
binary storage device capable of storing one bit of information.
The types of flip flops
are
- D Flip Flop
- T Flip Flop
- JK Flip Flop
- SR Flip Flop
- Master-Slave Flip Flop
4.1 D
FLIP FLOP:
SYMBOL:
EQUATION:
Q
(t + 1) = D
EXCITATION
TABLE:
|
Q(t)
|
Q(t+1)
|
D
|
|
0
|
0
|
0
|
|
0
|
1
|
1
|
|
1
|
0
|
0
|
|
1
|
1
|
1
|
PROGRAM:
module DFF ( Q, D ,CLK);
output Q ;
reg Q ;
input D,CLK ;
always @ (posedge CLK)
Q = D;
endmodule
4.2 T
FLIP FLOP:
SYMBOL:
EQUATION:
Q
(t + 1) = TQ’ + T’Q
EXCITATION
TABLE:
|
Q(t)
|
Q(t+1)
|
T
|
|
0
|
0
|
0
|
|
0
|
1
|
1
|
|
1
|
0
|
1
|
|
1
|
1
|
0
|
PROGRAM:
module t_flip_flop ( t
,clk ,reset ,dout );
output dout ;
reg dout ;
input t ;
wire t ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0;
always @ (posedge (clk))
begin
if (reset)
dout <= 0;
else
begin
if (t)
dout <= ~dout;
end
end
endmodule
4.3 JK
FLIP FLOP:
SYMBOL:
EQUATION:
Q
(t + 1) = JQ’ + J’Q
EXCITATION
TABLE:
|
Q(t)
|
Q(t+1)
|
J
|
K
|
|
0
|
0
|
0
|
X
|
|
0
|
1
|
1
|
X
|
|
1
|
0
|
X
|
1
|
|
1
|
1
|
X
|
0
|
PROGRAM:
module JK_flip_flop ( j
,k ,clk ,reset ,q ,qb );
output q ;
reg q ;
output qb ;
reg qb ;
input j ;
wire j ;
input k ;
wire k ;
input clk ;
wire clk ;
input reset ;
wire reset ;
always @ (posedge
(clk))
begin
if (reset)
begin
q <= 0;
qb <= 1;
end
else
begin
if (j!=k)
begin
q <= j;
qb <= k;
end
else
if (j==1 &&
k==1)
begin q <= ~q;
qb <= ~qb;
end
end
end
endmodule
4.4 SR
FLIPFLOP:
SYMBOL:
EQUATION:
Q(t
+ 1) = S + R’Q
EXCITATION
TABLE:
|
Q(t)
|
Q(t+1)
|
S
|
R
|
|
0
|
0
|
0
|
X
|
|
0
|
1
|
1
|
0
|
|
1
|
0
|
0
|
1
|
|
1
|
1
|
X
|
0
|
PROGRAM:
module sr_flip_flop ( s
,r ,clk ,reset ,q ,qb );
output q ;
reg q ;
output qb ;
reg qb ;
input s ;
wire s ;
input r ;
wire r ;
input clk ;
wire clk ;
input reset ;
wire reset ;
always @ (posedge
(clk))
begin
if (reset)
begin
q <= 0;
qb <= 1;
end
else
begin
if (s!=r)
begin
q <= s;
qb <= r;
end
else
if (s==1 &&
r==1)
begin
q <= 1'bZ;
qb <= 1'bZ;
end
end
end
endmodule
4.5 MASTER
SLAVE FLIP FLOP:
We can use any type of flip flop. For example i have taken D flip flop. A D flip flop takes only a single input, the D (data) input. The master-slave configuration has the advantage of being edge-triggered, making it easier to use in larger circuits, since the inputs to a flip-flop often depend on the state of its output.
The circuit consists of two D flip-flops connected together. When the clock is high, the D input is stored in the first latch, but the second latch cannot change state. When the clock is low, the first latch's output is stored in the second latch, but the first latch cannot change state.
The result is that output can only change state when the clock makes a transition from high to low.
The circuit consists of two D flip-flops connected together. When the clock is high, the D input is stored in the first latch, but the second latch cannot change state. When the clock is low, the first latch's output is stored in the second latch, but the first latch cannot change state.
The result is that output can only change state when the clock makes a transition from high to low.
DIAGRAM:
PROGRAM:
module master_slave_ff ( din ,clk
,reset ,dout );
output dout ;
input din ;
input clk ;
input reset ;
wire s;
wire in_clk;
assign in_clk = ~clk ;
d_flip_flop u0
(.din(din),.clk(clk),.reset(reset),.dout(s));
d_flip_flop u1
(.din(s),.clk(in_clk),.reset(reset),.dout(dout));
endmodule
In next session we are going to see about latches.
