2. ADDERS

addition is a heart of modern computation. For addition adders plays a vital role in multipliers, subractors and DSP Applications. For the low power and fast applications adders are designed. They are many types of adders such as

·        Half Adder
·        Full Adder
·        Ripple Carry Adder
·        Carry Look Ahead adder
·        Carry Select adder
·        Carry Save adder
·        Kogge Stone adder
·        Ling adder
·        SPST adder

2.1 HALF ADDER:

Half Adder has 2 inputs and 2 outputs. The inputs are ‘a’ and ‘b’, and the outputs are ‘sum’ and ‘carry’. Let us see the logical equation of this circuit.

Sum = a xor b

Carry = a and b

Let us see the Verilog and VHDL coding of Half Adder.

Verilog:

Program:

module half_adder(sum,carry,a,b);

output  sum,carry;

input a,b;

assign sum = a^b;

assign carry = a&b;

endmodule

VHDL:

PROGRAM:

library IEEE;

use ieee.std_logic_1164.all;

entity half_adder is

port( a, b : in std_logic;

sum, carry : out std_logic );

end half_adder;

architecture behavorial of half_adder is

begin

sum <= A xor B;

carry <= A and B;

end;

end behavorial;

2.2 FULL ADDER:

Full Adder has 3 inputs and 2 outputs. The inputs are ‘a’, ‘b’, and ‘cin’ (input carry) and the outputs are ‘sum’ and ‘carry’ which is output carry. We can also design the full adder with the help of half adders. Let us see the logical equation of this circuit.

Sum = a xor b xor cin

Carry = (a and b) or (cin and (a xor b))

Let us see the Verilog and VHDL coding of Full Adder.

Verilog:

Program:

module full_adder(sum,carry,a,b,cin);

output  sum,carry;

input a,b,cin;

wire carry1,carry2,sum1;

half_adder g1(sum1,carry1,a,b);

half_adder g2(sum,carry2,cin,sum1);

or g3(carry,carry1,carry2);

endmodule

VHDL:

PROGRAM:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

entity fulladd is

    port(

        a     : in    std_logic;

        b     : in    std_logic;

        cin  : in    std_logic;

        sum   : out   std_logic;

        carry: out   std_logic);

end fulladd;

architecture behv of fulladd is

begin

    sum <= a xor b xor cin;

    carry <= (a and b) or (cin and (a or b));

end behv;

2.3 Ripple carry adder

The combination between two or more full adders is called ripple carry adder. This circuit has the input carry C0 and the binary inputs such as X0,Y0, X1,Y1, X2,Y2, X3,Y3 and the outputs are S0, S1, S2, S3 and output carry C4.

The layout of a ripple-carry adder is simple, which allows for fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder.

Verilog:

Program:

module rca(sum,carry,a,b,cin);

output [3:0]sum;

 output carry;

input [3:0]a,b;

input cin;

wire d1,d2,d3;

full_adder g1 (sum[0],d1,a[0],b[0],cin);

full_adder g2 (sum[1],d2,a[1],b[1],d1);

full_adder g3 (sum[2],d3,a[2],b[2],d2);

full_adder g4 (sum[3],carry,a[3],b[3],d3);

endmodule

VHDL:

PROGRAM:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rca is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

       b : in STD_LOGIC_VECTOR (3 downto 0);

       cin : in STD_LOGIC;

       sum : out STD_LOGIC_VECTOR (3 downto 0);

       carry: out STD_LOGIC);

end rca;

Architecture Behavioral of rca is

component fulladd

Port ( a : in STD_LOGIC;

       b : in STD_LOGIC;

       cin : in STD_LOGIC;

       sum : out STD_LOGIC;

       carry : out STD_LOGIC);

end component;

signal c1,c2,c3: STD_LOGIC;

begin

ad0:fulladd port map(a(0),b(0),cin,sum(0),c1);

ad1:fulladd port map(a(1),b(1),c1,sum(1),c2);

ad2:fulladd port map(a(2),b(2),c2,sum(2),c3);

ad3:fulladd port map(a(3),b(3),c3,sum(3),carry);

end Behavioral;

2.4 CARRY LOOKAHEAD ADDER

To reduce the propagation delay carry look-ahead adders are used instead of ripple carry adder. Here the full adder logic equations are used. If the auxiliary functions, pi and gi called the propagate and generate signals, the sum output respectively are defined as follows.

pi = ai xor bi,

gi = ai and bi

si = ai xor bi xor ci

ci+1= gi or (pi and ci) .

Verilog:

Program:

module clha(sum,carry,a,b,cin);

output [3:0]sum;

output carry;

input [3:0]a,b;

input cin;

wire p0,p1,p2,p3,g0,g1,g2,g3;

wire c0,c1,c2,c3;

assign p0=a[0]^b[0],

           p1=a[1]^b[1],

           p2=a[2]^b[2],

           p3=a[3]^b[3];

assign g0=a[0]&b[0],

            g1=a[1]&b[1],

            g2=a[2]&b[2],

            g3=a[3]&b[3];

assign c1=g0|(p0&cin),

           c2=g1|(p1&g0)|(p1&p0&cin),

           c3=g2|(p2&g1)|(p2&p1&g0)|(p2&p1&p0&cin),

          c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&cin);

assign sum[0]=p0^cin,

            sum[1]=p1^c1,

            sum[2]=p2^c2,

            sum[3]=p3^c3;

assign carry=c4;

endmodule

VHDL:

PROGRAM:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clha is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

       b : in STD_LOGIC_VECTOR (3 downto 0);

       cin : in STD_LOGIC;

       yout : out STD_LOGIC_VECTOR (3 downto 0);

       cout : out STD_LOGIC);

end clha;

Architecture Behavioral of clha is

Signal p0, p1, p2, p3, g0, g1, g2, g3: STD_LOGIC;

Signal c0, c1, c2, c3: STD_LOGIC;

begin

p0 <= a(0) xor b(0);

p1<= a(1) xor b(1);

p2<= a(2) xor b(2);

p3<= a(3) xor b(3);

g0<= a(0) and b(0);

g1<= a(1) and b(1);

g2<= a(2) and b(2);

g3<= a(3) and b(3);

c1<=g0 or (p0 and cin);

c2<=g1 or (p1 and g0) or (p1 and p0 and cin);

c3<=g2 or (p2 and g1) or (p2 and p1 and g0) or (p2 and p1 and p0 and cin);

c4<=g3 or (p3 and g2) or (p3 and p2 and g1) or (p3 and p2 and p1 and g0) or (p3 and p2 and p1 and p0 and cin);

sum(0) <= p0 xor cin;

sum(1) <= p1 xor c1;

sum(2) <= p2 xor c2;

sum(3) <= p3 xor c3;

carry <= c4;

end

end behavorial

Let us see the other type of adders in next session